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Wave pipeline effect on LUT-based FPGA architectures

Publicado en:ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 45-50 - 1996-01-01 (), DOI: 10.1145/228370.228377

Autores: Boemo EI; Lopez-Buedo S; Meneses JM

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Resumen

The wave pipeline effect is based on the equalization of all path delays in order to allow several 'waves' of data to travel along the circuit with a separation several times smaller than the maximum combinational delay of the circuit. The construction of wave pipelines requires gates and buffers with data-independent delay, and a well-characterized interconnection network delay model, in order to allow the equalization process to be managed by the designer. These features are inherently present in several RAM-based FPGAs architectures. Look-up tables (LUTs) permit the delay of digital blocks with different types of gates or different logic depth to be equalized; moreover, the delay of a FPGA interconnection network is completely parameterized and is a priori known. This paper describes a LUT-based wave pipeline array multiplier manually implemented using a Xilinx chip. The results show that, even for a single-phase non-skewed clocking strategy, a throughput as high as 85 MHz (measured) can be achieved, with 8 waves running in a 13-LUT logic depth combinational array with registered I/O, producing an initial latency of 9 clock cycles. For the FPGA architecture and the topology selected, such a large throughput/latency ratio would be impossible using classical pipelining.

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