SUTTER CAPRISTO, GUSTAVO DANIEL
iMarina ID: 04-260809Códigos de identificación
Departamento Universitario
Tecnología Electrónica y de las Comunicaciones. Universidad Autónoma de Madrid. Ciudad Universitaria de Cantoblanco. Madrid. 28049
Centro
Escuela Politécnica Superior. Universidad Autónoma de Madrid. Ciudad Universitaria de Cantoblanco. Madrid. 28049
Grupo
High Performance Computing And Networking. Universidad Autónoma de Madrid. Ciudad Universitaria de Cantoblanco. Madrid. 28049
Área de Conocimiento
Arquítectura Y Tecnología De Computadores
Timeline
abril de 2005
Doctorado: Doctor/a
Universidad Autónoma de Madrid
Titulado superior / Grado: INGENIERO EN INFORMÁTICA
Reconocimientos Docentes
Quinquenios
3
Año último Quinquenio: 2017
Reconocimientos Investigación
Sexenios
2
Año último Sexenio: 2017
Timeline
diciembre de 2018
Miembro
Universidad Autónoma de Madrid. High Performance Computing And Networking
2018 -
junio de 2012
E. POLITÉCNICA SUPERIOR SUBDIR. RELACIONES EXTERNAS
Universidad Autónoma de Madrid
2012 - 2014
septiembre de 2010
Profesor Contratado Doctor LOU
Universidad Autónoma de Madrid. Tecnología Electrónica y de las Comunicaciones
2010 -
octubre de 2006
Profesor Ayudante Doctor LOU (020020061). Tecnología Electrónica y de las Comunicaciones
Universidad Autónoma de Madrid
2006 - 2010
octubre de 2006
Profesor Ayudante Doctor LOU. Tecnología Electrónica y de las Comunicaciones
Universidad Autónoma de Madrid
2006 - 2010
octubre de 2004
Ayudante Universidad LOU (020020060). Ingeniería Informática
Universidad Autónoma de Madrid
2004 - 2006
octubre de 2002
Ayudante Universidad LOU (020020060) . Ingeniería Informática
Universidad Autónoma de Madrid
2002 - 2004
Publicaciones en Altmetrics
| 2019 | Towards 100 GbE FPGA-Based Flow Monitoring | |
| 2019 | Limago: An FPGA-based open-source 100 GbE TCP/IP stack | |
| 2019 | Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable dev... | |
| 2019 | FPGA-based TCP/IP checksum offloading engine for 100 Gbps networks | |
| 2018 | Submicrosecond latency video compression in a low-end FPGA-based system-on-chip | |
| 2018 | An FPGA-based approach for packet deduplication in 100 gigabit-per-second networ... | |
| 2018 | A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet li... | |
| 2016 | FPGA-based encrypted network traffic identification at 100 Gbit/s | |
| 2016 | Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring... | |
| 2016 | Accurate and affordable packet-train testing systems for multi-gigabit-per-secon... | |
| 2016 | Leveraging open source platforms and high-level synthesis for the design of FPGA... | |
| 2014 | TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte tr... | |
| 2014 | Bridging the Gap between Hardware and Software Open Source Network Developments | |
| 2013 | Accurate and flexible flow-based monitoring for high-speed networks | |
| 2013 | Efficient elliptic curve point multiplication using digit-serial binary field op... | |
| 2013 | FPGA acceleration using high-level languages of a Monte-Carlo method for pricing... | |
| 2012 | Finite-Field Arithmetic | |
| 2012 | Basic Building Blocks | |
| 2012 | Virtualization of reconfigurable coprocessors in HPRC systems with multicore arc... | |
| 2012 | Embedded Systems Development: Case Studies | |
| 2012 | Partial Reconfiguration on Xilinx FPGAs | |
| 2012 | Dividers | |
| 2012 | EDA Tools | |
| 2012 | Special Topics of Data Path Synthesis | |
| 2012 | Electronic Aspects of Digital Design | |
| 2012 | Architecture of Digital Circuits | |
| 2012 | Other Operations | |
| 2012 | Decimal Operations | |
| 2012 | Floating Point Arithmetic | |
| 2011 | Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosyste... | |
| 2011 | Selected papers from the Southern Programmable Logic Conference (SPL2010) | |
| 2011 | High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulation... | |
| 2011 | Experiences applying framework-based functional verification to a design for pro... | |
| 2011 | A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor | |
| 2010 | High-speed FPGA 10's complement adders-subtractors | |
| 2010 | Decimal division: algorithms and FPGA implementations | |
| 2010 | Efficient FPGA modular multiplication and exponentiation architectures using dig... | |
| 2009 | A FPGA IEEE-754-2008 decimal64 floating-point multiplier | |
| 2009 | DECIMAL ADDITION IN FPGA | |
| 2009 | FPGA Implementations of BCD Multipliers | |
| 2009 | HIGH SPEED FIXED POINT DIVIDERS FOR FPGAS | |
| 2009 | FAST RADIX 2 boolean AND K DIVIDERS FOR FPGAS | |
| 2009 | Decimal adders/subtractors in FPGA: Efficient 6-input LUT implementations | |
| 2009 | Vaccinia virus-mediated inhibition of type I interferon responses is a multifact... | |
| 2008 | Selected Papers from SPL 2008: Programmable Logic and Applications | |
| 2008 | Elliptic-curve point-multiplication over GF(2(163)) | |
| 2007 | AxB not equal BxA in terms of power consumption: Some examples on FPGA | |
| 2007 | Viability study of soft-processor usage for electronic collimation control in me... | |
| 2006 | Hardware implementation of finite-field division | |
| 2006 | Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded Systems | |
| 2005 | Finite field division implementation | |
| 2004 | Comparative Study of SRT-Dividers in FPGA | |
| 2004 | Power Aware Dividers in FPGA | |
| 2002 | Low-Power FSMs in FPGA: Encoding Alternatives | |
| 2002 | A Tool for Activity Estimation in FPGAs | |
| 2002 | FSM Decomposition for Low Power in FPGA | |
| 1998 | An experimental study of high speed orthogonal cutting |
Temáticas más frecuentes
Temáticas
Proyectos participados
Dirección y participación en proyectos
IP
NO IP
Grupos, Redes
High Performance Computing And Networking
Asignatura / Curso
Actividad docente
Tesis Dirigidas
3
Centros
Universidad Autónoma de Madrid
Colaboración institucional últimos 5 años
